Digital Logic Design Using Verilog by Vaibbhav Taraate

Author:Vaibbhav Taraate
Language: eng
Format: epub
Publisher: Springer India, New Delhi

The RTL Verilog codes discussed in Chaps. 1–8 can be targeted on the suitable FPGA design by using the design guidelines for the FPGA. Following are the few design guidelines need to be followed while designing by using FPGAs.

9.7.1 Verilog Coding Guidelines

Guidelines for using Verilog to implement efficient RTL are listed in this section and it is always recommended to use these guidelines during RTL design phase. Among these, few guidelines are mainly described with reference to Verilog Stratified Event Queue discussed in Chaps. 4 and 6.

Download

Copyright Disclaimer:
This site does not store any files on its server. We only index and link to content provided by other sites. Please contact the content providers to delete copyright contents if any and email us, we'll remove relevant links or contents immediately.